Here are the definitive copies of my recent publications in PDF form.
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Send comments to Steve GolsonFlow Engineering for Physical Implementation: Theory and Practice by Steve Golson and Pete Churchill
Abstract: EDA tools are never used in isolation. Rather, multiple tools are combined into a sequence called a flow. Furthermore an elaborate infrastructure is required to support and enable flow execution. This flow infrastructure includes directory organization, configuration management, compute servers, desktop machines, job control, license administration, dependency management, operating systems, team communication, error reporting, and libraries of all sorts. Oh, and of course the EDA tools themselves. While EDA tools come with documentation and user guides, and many of the components of the flow infrastructure have standalone documentation, there is virtually no manual or reference guide or checklist available to aid in the creation and improvement of a flow. Join two veteran consultants, each with over 20 years experience in IC design, as we discuss the theory and practice of flow engineering: the design of flow infrastructure and the flows themselves.
Here are the slides as PDF and PowerPoint. It may be hard to follow when you don't have Pete and me making the presentation, and you'll probably miss the jokes. Also there are some provocative statements (slide 28 comes to mind). You have to hear the talk to understand the context. Really, we love EDA tools.
You can find lots more about this presentation at the flowMaker website.
Abstract: Engineering Change Orders or ECOs are all too prevalent in ASIC design. Unfortunately there are few tools that directly support these "last minute" changes to a design. So it's left to us humans to figure out a solution.
This paper will cover the ad hoc solutions that have been developed for implementing ECOs. Topics to be covered:
- basic definitions: the types of ECOs
- where in the flow to make the change
- advanced netlist dissection techniques
- implementing large ECOs using thousands of gates
- equivalence checking: your best friend
- back-end issues
- why ECOs are really a management problem, and how to deal with it
This won the Best Paper Award.
Abstract: This paper will investigate the pros and cons of synchronous and asynchronous resets. It will then look at usage of each type of reset followed by recommendations for proper usage of each type.
I recommend you use synchronous resets as much as possible.
The Future of ASIC Design(ers) by Steve Golson
This year I was honored to be invited as Guest Speaker, and these are the slides from the presentation I gave. It's a bit harder to follow when you don't have me talking to each slide, but perhaps you can still get some of the jokes :-) The astute reader will note some overlap with my SNUG 2000 presentation. I prefer to call it design reuse.
Abstract: The debate over verification continues unabated over how critical a role it plays in the overall design process. In some circles, it is viewed as essential and valuable. Even so, there are questions over which verification tools are necessary and what tools work. Project teams need to determine whether to spend more time on verification, or less time. As a result, they must evaluate the relative contribution to a design's success made by design engineers versus verification engineers. Some design stalwarts wonder if an entire team to correct the mistakes of the designer isn't overkill. Still others wonder just how interesting or creative the role or verification engineer really is.
Should the role of verification engineer be a career goal? When a project team ramps up, who's hired first, designers or verification engineers? The panel will take a hard look at the true value of verification and offer some candid answers.
I was the token "design engineer" on the panel . One of these days I'll write down my thoughts about architecture, design, and verification.
Abstract: A wealth of new hierarchical compile strategies have become available in the last few years. This paper will compare area, speed, and compile time for several large designs using a variety of hierarchical compile strategies: top-down compile, top-down simple compile, bottom-up with default constraints, bottom-up with hand-crafted constraints, and ACS (Automated Chip Synthesis).
You can download a tarball of all of the scripts, constraint files, and Makefiles described in the paper.
Get more information about the picoJava-II design from Sun Microsystems.
Here are Perl scripts for doing scatter_plots and ratio_plots. These scripts take timing reports from Synopsys Design Compiler and generate commands for gnuplot.
My SNUG 1999 paper used similar plotting techniques.
Levels of Abstraction: The History of Custom MOS Design by Steve Golson
For the Tenth SNUG in 2000, Kurt Baty organized a panel discussion that reviewed progress in synthesis, simulation, and EDA tools in general over the past decade. Here are the slides from my presentation covering the history and possible future of ASIC design.
Abstract: Wireload models are like the weather. Many people talk about them, but not many people do anything about them! This paper will explore some of the myths and realities of wireload models:
- why wireload models are important, and why nobody understands them
- why your intuition is wrong
- why you shouldn't trust your silicon vendor
- why floorplanning sometimes doesn't matter
- why having an accurate wireload model is a bad idea
A technique for measuring the quality of wireload models will be described. Real-world results will be discussed. Cool graphics will be shown. A desperate plea for future work will be given.
This won the Best Paper Award. Yes, that makes three years in a row.
Here are Perl scripts for doing scatter_plots and ratio_plots. These scripts take timing reports from Synopsys Design Compiler and generate commands for gnuplot.
My SNUG 2001 paper uses similar plotting techniques.
Abstract: We have developed a methodology to automatically synthesize large hierarchical designs. This methodology combines the advantages of bottom-up compilation with top-down rebudgeting.
Starting with only the Verilog source code, all required makefiles, synthesis scripts, and constraint files are automatically derived. An overconstraining leaf module time-budgeting method is used for initial synthesis.
For subsequent synthesis runs, a top-level constraint file (perhaps manually generated) is used to automatically create constraints for leaf modules. Timing information is extracted from top-level timing reports. True timing budgets can be generated while avoiding the limitations of characterize.
This won the Best Paper Award.
My SNUG 1997 paper introduced dc_perl. Here's the updated version of the dc_perl script that includes the do_the_right_thing command.
dc_perl is very simple and very fragile. It was mostly a proof of concept. If you are considering using Perl and Design Compiler (or any other Synopsys tool) I recommend you have a look at Jeff Solomon's excellent Perl module SPP.
The road ahead in CPLD & FPGA design methodology (panel)
I was the token ASIC designer on this panel. Here are the slides I presented.
Abstract: Is there a command that you wish dc_shell had?
By using the Perl interpreter as a "wrapper" around dc_shell, powerful extensions to dc_shell can be created. dc_shell commands can be generated by Perl, and the results analyzed by Perl in real time (not post-processed). Further dc_shell commands can be algorithmically generated by Perl based on the given results.
The user interface is just like dc_shell, but with user-defined extensions. This approach is particularly suited for complex synthesis problems that currently require lots of post-processing or tedious human analysis.
This won the Best Paper Award.
Here's the original dc_perl distribution. See the SNUG 1998 paper for further work with dc_perl.
Abstract: You can make dc_shell do amazing and wonderful things.
Many of the complaints and workarounds explored in this paper have been addressed in later versions of Design Compiler. Tcl is a huge improvement as well.
Here is the buffer tree insertion script buf.ss that was described in my presentation at the conference.
Abstract: Designing a synchronous finite state machine (FSM) is a common task for a digital logic engineer. This paper will discuss a variety of issues regarding FSM design using Synopsys Design Compiler. Verilog and VHDL coding styles will be presented. Different methodologies will be compared using real-world examples.
This has been a very popular paper, although it really needs to be updated.
Abstract: One-hot state machines use one flop per state. They are particularly suited to today's register-rich FPGA architectures. This paper will discuss the advantages of one-hot state machines including ease of design, simple timing analysis, and high clock rates. An SBus master/slave interface will be used as a design example. VHDL and Verilog coding styles will be discussed.
Most of this is pretty dated.
A 2K byte fully-associative cache memory with on-chip DRAM control by Scott Griffith and Steve Golson
Abstract: A 2Kbyte cache memory with on-chip DRAM control has been built. The fully-associative write-back write-allocate cache is organized as 128 lines by 16 bytes. The part directly connects to and controls an array of 1 Mb DRAMs forming a 4Mbyte parity-checked memory subsystem. Zero wait state operation of the Intel 80386 microprocessor at 25MHz is supported. Fabricated in a 2µ CMOS process, the 374x383 mil die contains 172K transistors.
The copyright for this paper is owned by IEEE so I can't put a PDF here. A small number of reprints are available, and I'll send you one if you email me and ask for it.
This chip project was codenamed Kali and was designed as the memory controller for the Sun 386i workstation (codename Roadrunner). It inspired John Sundman to write a wonderful award-winning hacker-thriller novel Acts of the Apostles.